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United States-based IBM has announced what it describes as the world’s first sub-one-nanometer semiconductor chip technology, unveiling a new three-dimensional transistor architecture called NanoStack for the 0.7-nanometer, or seven-angstrom, node. Revealed on June 25, 2026, the research breakthrough marks a significant step in the global race to produce smaller, faster and more energy-efficient microchips, and is positioned by IBM as a foundation for the next decade of semiconductor innovation and atomic-level chip design. The company says the NanoStack architecture builds directly on nanosheet transistor technology that it helped pioneer as the industry approached the physical limits of traditional planar designs, enabling further miniaturization while maintaining performance and control over electrical currents at extremely small scales. IBM’s technical disclosures indicate that the 0.7-nanometer NanoStack architecture can pack nearly 100 billion transistors on a silicon die roughly the size of a human fingernail, nearly doubling the transistor density of its 2021 two-nanometer chip technology, which previously held the density record. The company projects that chips manufactured on the NanoStack 0.7-nanometer node will deliver up to a 50 percent improvement in processing performance or up to a 70 percent reduction in energy consumption compared with existing two-nanometer node designs. IBM also reports an approximate 40 percent improvement in static random-access memory, or SRAM, scaling, a gain that it says is particularly important for artificial intelligence workloads that depend on large quantities of high-bandwidth, high-efficiency memory located close to computing cores to mitigate data transfer bottlenecks.

Prepared by Jonathan Pierce and reviewed by editorial team.